1. Field of the Invention
The invention in general relates to integrated circuit memories and more particularly with such memories in which two or more portions of the bit lines are isolated from one another during an access cycle to improve performance.
2. Statement of the Problem
Integrated circuit memories generally contain a two dimensional array of storage cells arranged in rows and columns. A common architecture is to connect all cells in a row to a common row line, often referred to as the "word line" and all cells in a column to a common column line often called the "bit line" or "digit line". In this architecture, the row line provides a signal which enables cells to receive or output a data signal and the column line provides the input or output line on which the signal is transferred. An individual cell is addressed via a row decoder that selects a row to be addressed and a column decoder which selects a column to be addressed, thereby selecting one particular cell at the corresponding row and column location. The cell is accessed by placing an enable signal on the row line in the row associated with the cell and reading or writing a signal on the column line associated with the cell.
Integrated circuit memories are also generally binary logic circuits in which information is stored and transferred as voltages representing complementary logic values that are alternately referred to as "true and false", "logic 1 and logic 0", or "logic high and logic low". Typically a voltage of 5 volts may represent the logic 1 state while a voltage of zero volts represents the logic 0 state. Because of the constraints of resistance, capacitance etc. the individual voltages input to or output on the column lines by individual cells are usually at some intermediate voltage. Thus subcircuits are associated with the column lines of integrated circuit memories to pull the high voltage values up to, or as close as possible to, the full logic 1 voltage, for example 5 volts, and to pull the low voltages down to as close to the logic 0 voltage, for example 0 volts, as possible. These subcircuits are commonly referred to as sense amplifiers. A common architecture utilizes a separate pull down subcircuit, referred to as an N-sense amplifier, to pull the low signals down to the logic 0 voltage, and a separate pull up subcircuit, referred to as a P-sense amplifier, to pull the high voltages up to the logic 1 voltage.
The invention to be disclosed herein is particularly applicable to an architecture used in dynamic random access memories (DRAM) and video random access memories (VRAM). In this architecture the individual memory cell comprises a transistor and a capacitor connected in series. One side of the capacitor is connected to a reference voltage, and the other side is connected to the column line through the transistor. The gate of the transistor is connected to the row line. Information is stored in the form of charge on the capacitor, which charge is input and output via the column line and gated by the row line acting on the transistor gate. There are tens or even hundreds of such cells connected to each column line. The column lines are organized into pairs with one N-sense amplifier and one P-sense amplifier associated with each pair. The N-sense amplifiers and P-sense amplifiers are connected across the pairs, with one column line going low and the other going high when one of the pairs of lines is addressed. The attachment of the transistor gates to row lines is staggered with the cells associated with adjacent pairs of column lines belonging to different rows so that the transistor which gates one of each associated pair will be off when a cell on the other of the pair is being addressed. That is, when a particular cell is addressed, the column line it is attached to will go high or low, depending on the cells content; the other column line or the pair will go to the opposite logic value. When the read or write cycle is over, the pairs are shorted together, which quickly brings them to a mid-voltage level, resetting them for the next cycle. In this way the pairing of the lines results in faster cycling of the circuit as a whole. Since the connection of the cells to the row lines are staggered, the transistor gates associated with the one of the line pair that is not being addressed are always off and the information in the cells is not affected by the column line of the non-addressed cells going high or low. This architecture is referred to as "divided bit line sensing". A common arrangement of the various parts of the circuit in the divided bit line sensing approach is to locate the column decoder and DRAM input and output terminals at one end of the column lines, the P-sense amplifiers at the other end of the column lines, and the N-sense amplifiers at the center of the column lines thereby dividing each the column lines into two halves, one half of the line extending between the N-sense amplifier and the column decoder and the other half extending between the N-sense amplifier and the P-sense amplifier. In VRAM there is also a sequential-access memory (SAM) port connected to the column lines on the side of the P-sense amplifier opposite the column decoder.
As is well-known, integrated circuit memories are generally mass produced by fabricating hundreds of identical circuit patterns on a single semiconducting wafer, which wafer is subsequently sawed into hundreds of identical dies or chips. The advantages of building integrated circuits with smaller individual circuit elements so that more and more circuitry may be packed on a single chip are well-known: electronic equipment becomes less bulky, reliability is improved by reducing the number of solder or plug connections, assembly and packaging costs are minimized, and improved circuit performance, in particular higher clock speeds. However, the smaller the size of the individual cell, the smaller the size of the individual electrical components in the cell, and the smaller the electrical signals associated with them. As more and more individual storage cells are paced unto a single chip, the length of the column lines connecting the individual cells to the amplifiers becomes longer and longer as compared to the individual cell size, and the capacitance associated with the lines becomes larger. This means that the signal transferred to the column line from an individual cell will become even smaller as the capacitance of the line absorbs the charge, and further that the time for developing a useful signal level on the line will increase. As is well known, speed is an important factor in such memories, since the faster the cells can be read, the faster is the computer of which the memory is a part, and the more operations the computer can do. Thus a number of enhancements have been made to DRAM and VRAM architecture to increase the signal level and amplifier response time. Several such enhancements are described in U.S. Pat. Nos. 4,748,349 and 4,636,987. The former patent describes a circuit which boosts the voltage on the row line and thus the gate of the gating transistors to a value above the high logic voltage of the circuit. This permits the full high logic voltage to be placed on the cell capacitor, since the threshold voltage drop across the gating transistor is eliminated. The latter patent describes an architecture in which each N-Sense amplifier is connected to each of the four column line pair halves associated with it through an isolation transistor. The gates of the isolation transistors are connected to a timing signal which isolates the N-sense amplifier from the column line pair halves on the opposite side of the N-sense amplifier from the row that is being addressed. That is, when the row being addressed is on, say, the left side of the N-sense amplifier, the isolating transistors connecting the N-sense amplifier to the left halves of the column line pair are on while the isolating transistors on connecting the N-sense amplifier to the halves on the right side of the N-sense amplifier are off. Thus the N-sense amplifier is connected to only half of the full column line during the time the N-sense amplifier signal is developing, which doubles the signal that the addressed cell develops at the N-sense amplifier. However, this architecture creates several disadvantages. First, for the cells on the opposite side of the N-sense amplifier from the P-sense amplifier, i.e. cells between the N-sense amplifier and the column decoder, the voltage developed at the P-sense amplifier must pull through the two isolation transistors, thus the voltage for these accesses can never be pulled to the full logic 1 voltage, but is down V.sub.T, the threshold voltage of the isolation transistors. This also results in a significantly lower voltage developed by the P-sense amplifier in half of the accesses Which either requires more stringent specifications in design and fabrication, and/or results in more defects and less reliability. Further, in order to prevent the voltage drop V.sub.T from being too large, the isolation transistors have to be natural threshold N-channel transistors. Since all the transistors in the DRAM or VRAM integrated circuit except these are high impedance transistors, this architecture requires an additional mask step in fabrication process, i.e. a natural threshold transistor mask step. Thus there is a need for a memory architecture that allows the full logic one voltage to be developed on both pairs of column line halves, allows the use of high impedance isolation transistors, and/or provides a more balanced voltage throughout the access cycle.
For many applications of integrated circuit memories, such as for portable computers and other battery powered intelligent devices, the amount of power available is limited. Thus it is important that sense amplifiers not only are fast and small, but also consume a minimum of power. The largest component of the total power used in DRAM's is the charging and discharging of the column lines. Since all bits on the selected row line during an access must be refreshed, all the column lines must be charged or discharged. In the prior art, the entire column line had to be charged or discharged in every access. Therefore there is a need for an integrated circuit memory design in which this charging and discharging of digit lines is limited. In sum, it would be highly desirable to have an integrated circuit memory architecture that not only increases the voltage developed at the N-sense amplifiers, increases the voltage developed by the P-sense amplifiers, provides a more balanced voltage curve throughout all accesses, and permits high impedance N-sense amplifier isolation transistors, but also decreases the power consumed by the memory circuit.
3. Solution to the Problem
The present invention solves the above problems by providing an improved P-sense amplifier architecture and, during an access of the column line halves nearest the data port, extends the isolation of the amplifier from the column line halves distal from the data port through the P-sense amplifier cycle. In the preferred embodiment the isolation is extended into the precharge cycle.
In one embodiment the invention employs two P-sense amplifiers per column line pair in the memory architecture. One P-sense amplifier is associated with each pair of column line halves. Preferably, one P-sense amplifier is located at the SAM end of the column line pair and another P-sense amplifier is located at the column decoder end of the column line pair.
More specifically, in DRAM, when the row being addressed is on the column decoder side of the N-sense amplifier, the isolation transistors on the SAM side of the N-sense amplifier remain off during both the N-sense and P-sense phases of the cycle, while in VRAM modes such as transfers and flash writes when the row being addressed is on the SAM side of the N-sense amplifier, the isolation transistors on the column decoder side of the N-sense amplifier remain off during both the N-sense and P-sense periods. During the refresh cycle, the isolation transistors on the opposite side of the N-sense amplifier from the row being addressed remains off during both the N-sense and P-sense periods.
Further, the actuation of the individual P-sense amplifiers is controlled by a timing signal so that the P-sense amplifiers associated with the column line pair halves that are isolated from the inputs/outputs during the P-sense cycle do not fire, thus not charging the associated column line halves and saving power.
Since, in this P-sense architecture the invention provides independent control of the high voltage on both sides of the N-sense amplifier, both halves of the column lines can be charged all the way to the full logic 1 voltage. This full voltage can then be written to all the storage cells, on both sides of the sense amplifier, providing substantially improved performance over the previous art.
In another embodiment, there is just one P-sense amplifier associated with each column line pair, but it is located adjacent the N-sense amplifier between the isolation transistors. With the isolation transistor timing described above, this architecture also results in the same power savings. It also provides a more balanced voltage throughout the cycle.